This invention relates generally to semiconductor memories such as dynamic random access memories (DRAMs), and more particularly the invention relates to a semiconductor memory including a single path data pipeline to accommodate column address signal (CAS) latency.
Semiconductor memories such as DRAMs and SRAMs are becoming more compact with increased circuit density. This has allowed the operating speed or clock frequency to increase. Thus, semiconductor memories are generally operable over a wide operating frequency range. However, a fixed amount of delay is experienced in such circuits such as the precharging of sense amplifiers prior to accessing bit lines and the development of data bits (DB,DB) on the sense amplifier output nodes and the transmission of the data bits to output pads. This can be due to column address latency or the time necessary in effecting an address to a column of the memory. Thus, some delay is required after a read command and the availability of data for the output pad to accommodate the CAS latency.
Heretofore, a first in/first out (FIFO) register has been employed to provide the required delay. Data is provided in parallel data paths with a circulating pointer sequentially selecting one of the data pads.
The present invention provides a simpler single path data pipeline to provide for variable CAS latency.